The Nervous System of Chips: How Arteris ($AIP) Is Powering the Chiplet Era

Chips are falling apart. Arteris is holding them together.

**PART 1: WHY CHIPS ARE BREAKING INTO PIECES (CHIPLETS)**

**System-on-Chip (SoC)**

Historically, PCs used separate chips for CPU, GPU, memory and I/O placed on a board. Today, engineers can fit all of them into one single piece of silicon, saving power and improving performance (shorter travel distance, lower overhead). This is the SoC, which is increasingly diverging into two frameworks: monolithic SoCs and chiplet-based SoCs.

**Monolithic SoC:** CPU, GPU, and other functional pieces all carved onto a single, large piece of silicon (a “die”). Performance-oriented with lower power consumption.

**Chiplet-Based SoC:** Instead of one large die, you build smaller “chiplets” and package them together (“multi-die”). The physical expression of this architecture is called a **System-in-Package (SiP)**.

[Source: imec](https://preview.redd.it/4txb3o056ahg1.png?width=1014&format=png&auto=webp&s=393584ca725b7c6690d504e86ce40df979a19302)

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**Why are we moving from monolithic SoCs to chiplet-based SoCs?**

* **Yield Economics:** Making one giant chip is both expensive and risky. A defect anywhere renders the whole chip unusable. By partitioning the chip into 8-10 smaller chiplets, defects can be identified and screened out at the die level during manufacturing, materially improving yield.
* **Reticle Limit:** Photolithography machines, which project circuit patterns via a reticle onto silicon wafers, have a maximum exposure field called the “reticle limit”. As leading accelerators grow in compute, they contain more transistors than can fit on a single reticle-sized die. To build high-end chips (Nvidia’s Blackwell, AMD’s Instinct, etc.), companies must use the chiplet approach to bypass the physical limits of photolithography. This is Moore’s Law hitting economic and physical limits. Chiplets are the architectural workaround.
* **Mixed-Node Integration:** Not every chip needs to be taped out using leading-edge photolithography (e.g. sub-7nm nodes enabled by ASML scanners). CPU/GPU chiplets can be fabricated on expensive 3nm nodes, while I/O chiplets can be produced on cheaper 16nm nodes. This drastically improves cost efficiency.
* **Heterogeneous “Lego Block” Flexibility:** If a company wants to upgrade the “AI accelerator” part of their chip, they may leave the other chiplets intact (CPU, memory, I/O). Chiplets allow for a mix-and-match business model that drastically speeds up innovation.

To understand where Arteris comes in, we need to understand (at least) one more framework: Network-on-Chip.

**Network-on-Chip (NoC)**

If the SoC is the brain, the NoC is the nervous system. It’s the communication fabric which moves data within and between processing units using packetized, routed traffic rather than shared wires (e.g. traditional bus architectures). As SoCs transition to chiplet-based architectures, interconnect complexity grows superlinearly. The challenge shifts from internal wiring to coordinating communication across a distributed system. A non-exhaustive list of challenges:

* **Heterogeneity**: Different chiplets speak different languages across different channels, requiring protocol translation and synchronization (ordering, arbitration, latency).
* **Coherence:** Every chiplet has its own local memory (cache). If Chiplet A changes a number in its cache, Chiplet B needs to know immediately. Data must stay consistent across dies, or the results become corrupt.
* **Quality of Service (QoS):** Different data packets have different priorities. For example, a sensor informing an autonomous vehicle's braking system must never be delayed by a background file transfer.
* **Physical Boundaries:** Moving data between chiplets involves crossing a physical gap (via micro-bumps and interposers). This introduces variations in latency and timing that must be actively managed to preserve data integrity.

**NoC has become a primary driver of system performance, and Arteris has emerged as the leading independent NoC architect.**

Arteris designs and licenses NoC IP that serves as the networking backbone of complex SoCs (intra-die) and chiplet-based systems (inter-die). Arteris does not sell chips. It sells embedded NoC IP that becomes part of the silicon itself and ships in every unit produced, along with the design and automation tools and software to implement them. In return, it receives upfront license fees for each design, ongoing support, and per-unit royalties as chips incorporating its NoC IP ship into production. More on the economics later.

Its technology is organized into three primary product suites:

* **FlexNoC:** A NoC for non-coherent data that provides scalable traffic across CPUs, GPUs, accelerators (e.g., ASICs), memory controllers, and I/O blocks within a die, while addressing heterogeneity and QoS. FlexNoC is widely adopted as the leading independent non-coherent interconnect IP and is frequently deployed alongside Ncore to separate non-coherent traffic from coherent domains (i.e. shared memory).
* **Ncore:** A cache-coherent NoC that maintains memory consistency across chiplets within a SiP, while also solving for heterogeneity and QoS. Ncore is recognized as the industry leading independent cache-coherent interconnect IP, given its position as the only independent silicon-proven solution that maintains full memory coherency across mixed architectures (e.g. ARM’s AMBA-CHI and RISC-V in the same package).
* **FlexGen (2025):** An automated NoC generation and optimization system that designs, configures, and validates FlexNoC and Ncore fabrics from high-level requirements, rather than manual RTL assembly. FlexGen translates usage, performance, and safety constraints into a concrete implementation, then iterates rapidly for correctness. FlexGen is cited to drastically reduce NoC design cycles (up to 10X) for large, heterogeneous, and chiplet-based systems.

Additional offerings include FlexWay (low-power SoCs), CodaCache (shared last-level cache), Magillem (tooling for complex SoC assembly), Functional Safety (ISO 26262 safety standards for automative SoCs), along with other add-ons.

**Arteris enables complex, heterogeneous systems to behave as a single coherent system, scaling performance by making data movement reliable and efficient as architectural complexity increases.**

**PART 2: THE SWITZERLAND OF INTERCONNECTS**

The chiplet market is expected to grow from $51.94 billion in 2025 to $157.23 billion by 2030, at a CAGR of 24.8%. Another projection suggests that the market will reach $411 billion by 2035. In 2026, the average high-end chip has moved from 1 large chip to 8–12 chiplets in a SiP. This change in design multiplies communication paths and failure modes, making the NoC a central architectural constraint.

An internal NoC is needed for most chiplets.

A system-level NoC is needed to manage the traffic between chiplets.

**As a result, the amount of usable Arteris IP per system increases significantly. Demand conditionally shifts from \~1–2 NoC instances per chip to upwards of 10+ NoC instances per system.**

Arteris earns royalties on shipped silicon based on the scope and complexity of the NoC IP licensed into a design. In chiplet-based SiPs, royalty value may be substantially higher as multiple NoC instances are deployed across dies.

This model is analogous to Arm’s CPU IP business. Arm is one of the most entrenched technologies in modern computing. Nearly all smartphones globally embed Arm-based CPUs (Apple, Qualcomm, Google, Samsung, etc.). While Arteris occupies a similar position at the interconnect layer, its moat does not yet approach the depth of Arm’s CPU IP moat, which is reinforced by decades of software ecosystem lock-in to reach near-ubiquitous adoption. However, as chiplet-based SoCs proliferate, Arteris’s competitive position can strengthen materially over time without requiring Arm-level ubiquity.

Arteris’s primary sources of revenue consist of:

* **Upfront IP license fees** paid when customers license NoC IP or related IP for a specific chip design or product family.
* **Per-unit royalties** earned on shipped silicon based on the scope, complexity, and deployment of Arteris IP within the design.
* **Maintenance and support fees** for updates, technical support, and access to new revisions.
* **Tool and software licenses fees** (e.g. Magillem) for design automation and system integration tools.
* **Safety and advanced feature add-ons** for safety packages (e.g. ISO 26262-certified IP)

Arteris’s business metrics are categorized as:

* **AV (Annual Contract Value) + Royalties**: Current run rate of licenses and production. (There's a "C" in there, but auto-mod thinks the full term is a ticker and removes the post)
* **RPO (Remaining Performance Obligations)**: Contracted future revenue from signed agreements with committed payments recognized over time.

Arteris generated $17.4 million in Q3 2025, up 18% YoY, with AV + Royalties of $74.9 million, up 24% YoY. RPO stood at $104.7 million, up 34% YoY, marking the first time RPO exceeded $100 million and signaling a growing contracted backlog. At the operating level, the company remained unprofitable on a GAAP basis, with ongoing operating losses due largely to sustained investment in R&D and go-to-market capabilities. Arteris ended the quarter with $56.2 million in cash, cash equivalents, and investments. Non-GAAP free cash flow was positive at $2.5 million. It has no financial debt.

Arteris is currently trading with a P/S of \~10X with a market cap of \~$670 million, reflecting expectations for growth as licensing activity builds and royalties materialize. Royalty revenue for Arteris lags licensing by several years, as NoC IP is licensed early in the design cycle and royalties are recognized only when chips reach production. Many recent design wins remain pre-production, suggesting current financials may understate the royalty potential for Arteris as these designs move from the licensing and design phase into mass production.

Meanwhile, Arteris has used targeted acquisitions to reinforce its business model by embedding itself more deeply across the design lifecycle. It acquired Magillem (2020) to provide customers with tooling for complex SoC assembly. The acquisition of Semifore (2023) added NoC performance modeling and analysis tools that allow customers to evaluate key metrics early in the chip design process. The acquisition of Cycuity (2026) added hardware security IP focused on isolation and protection, enabling secure data movement and fault containment across heterogeneous and safety-critical systems.

**As chiplet-based systems expand in size and complexity, building NoCs in-house becomes increasingly costly and inefficient, driving companies to license proven NoC IP from Arteris rather than absorb the burden of R&D and maintenance themselves.**

**PART 3: WHO’S USING THIS STUFF?**

A few examples for each segment:

**AI / Data Center / High-Performance Compute**

Chiplet-heavy, bandwidth-intensive, coherence-aware systems. Recent partnerships have validated Arteris’s significance as interconnect complexity becomes a central design and performance constraint.

* **AMD** using FlexGen IP for its next-generation AI chiplet designs, alongside proprietary Infinity Fabric in complex multi-die systems.
* **Tenstorrent** (led by Jim Keller) using Ncore IP in its AI accelerators.
* **Samsung** uses FlexNoC IP for use by its foundry customers.
* **Baidu** using FlexNoC IP for its custom silicon and AI accelerators.
* **Axelera AI** using FlexNoC IP to scale AI from edge computer vision to high-performance data centers.
* **Whalechip** using FlexNoC IP for advanced near-memory computing ASIC designs.

**Automotive / Vision / Safety**

Arteris has been cited to have approximately 70%-80% market share of the automotive ADAS (Advanced Driver Assistance Systems) SoC market as one of the only independent suppliers offering silicon-proven ISO 26262-ready NoC IP for safety-critical SoCs.

* **Mobileye (Intel)** using FlexNoC IP in vision and SoC designs.
* **Nextchip** using FlexNoC IP with Functional Safety for its automotive vision technology chips.
* **Bosch** using FlexNoC IP in multiple ISO 26262-compliant automotive projects and industrial automation.
* **BMW Group** using FlexNoC and Resilience Package for automotive AI/ML accelerator chips.
* **Renesas Technologies** using FlexNoC IP and Arteris multi-die technology broadly for ADAS with chiplet extensions.
* **MegaChips** using FlexNoC IP for automotive and embedded products.
* **NanoXplore** using FlexGen IP for aerospace and radiation-hardened embedded SoCs.
* **Black Sesame Technologies** using Ncore IP and FlexNoC IP for its next-gen intelligent driving silicon.

**Consumer / Edge / Embedded**

A fast-growing segment for Arteris, where FlexNoC IP is increasingly being adopted for AI and edge inference.

* **Texas Instruments** using FlexNoC IP for embedded processors and edge AI platforms.
* **NXP Semiconductors** using Ncore IP for embedded processors, automotive, and industrial SoCs.
* **Altera** using Arteris IP broadly, including FlexNoC IP, FlexGen IP, and Magillem to build FPGA solutions across cloud-to-edge applications targeting robotics and vision.
* **Toshiba** using Ncore IP for consumer and embedded SoCs.
* **Samsung & LG** using FlexNoC IP for smart home appliances and high-end consumer SoCs.
* **Rockchip** using FlexNoc IP in consumer tablets and IoT devices that utilizes FlexNoC to manage high-bandwidth multimedia traffic.

Companies rarely advertise their use of Arteris because NoC IP is a foundational infrastructure layer rather than a visible differentiator, and disclosing interconnect choices can expose sensitive architectural details. For example, Google and AWS often deploy custom silicon co-designed with Broadcom, yet the internal IP choices are rarely publicized. Meanwhile, Broadcom itself often incorporates third-party IP, including NoC IP solutions such as those from Arteris, in custom SoC designs for its clients. In recent earnings calls, management has referenced design wins with multiple large global technology companies, including CEO K. Charles Janac’s reference to an expanded reorder from a “top 5 technology company”.

We can also infer adoption indirectly from the chip architectures themselves (within a bounded confidence interval). The case for Google/Amazon as major potential Arteris clients:

* **Google** develops Tensor Processing Units (TPUs). Arteris has publicly marketed "NoC tiling with optional mesh topology for TPUs" as a primary use case for FlexNoC 5. Google has also co-developed TPUs with Broadcom. Broadcom likely uses third-party IP and may incorporate Arteris NoCs into the custom silicon they build for clients.
* **Amazon**’s newest Trainium3 and Graviton4 chips use advanced "die-to-die" connectivity. Arteris is one of the only commercial providers of the cache coherent interconnects (Ncore) required to make these massive server chips function as a single unit. Arteris’s Ncore represents one of the few commercially available, silicon-proven, independent solutions with cache-coherent interconnects.

**PART 4: WHERE THIS LEADS**

**Hyperscalers (AWS, Microsoft, Google, Meta)** often internalize NoC architecture when interconnect behavior is tightly coupled to proprietary workloads and system design. However, they also rely on partners such as Broadcom for silicon implementation, where proven NoC IP solutions from Arteris may be incorporated as complexity rises.

**Top-tier silicon vendors** (Nvidia, AMD) often build their own fabrics when interconnect is a core differentiator. These companies have a strategic incentive to internalize NoC development and can amortize the high R&D cost across many product generations (e.g. Nvidia’s use of NVLink/NVSwitch for GPU-centric, tightly coupled workloads). AMD uses a hybrid approach, maintaining proprietary fabric (e.g. Infinity Fabric) while licensing Arteris’s FlexGen IP to accelerate NoC design and validation, signaling that even top-tier vendors selectively adopt third-party tooling as scale and complexity increase.

**Mid-tier silicon vendors and specialist ASIC designers** ship complex SoCs and chiplet-based systems but cannot economically justify fully in-house NoC development across multiple generations. Their differentiation lies in compute blocks, system integration, or software, so they are structurally more inclined to license proven NoC IP to reduce risk and shorten schedules. This tier represents a core economic opportunity for Arteris where NoC is mission-critical, but building and sustaining NoC internally is not feasible. Qualcomm, Samsung, Altera, NXP, and others have broadly licensed and deployed Arteris IP across SoC programs.

**Automotive and safety-critical SoC designers** face strict ISO 26262 requirements and long lifecycles that make in-house NoC development costly to maintain. Arteris has already established a dominant position in automotive and ADAS with adoption by MobilEye, Bosch, BMW Group, Renesas Electronics, and many others. As autonomy and centralized vehicle compute scale, safety-compliant NoC IP accelerates time-to-market and enables broader deployment of ADAS and SDS.

**Why Arteris?**

Arteris operates in a competitive landscape that includes EDA vendors (who provide the software tools used to design, verify, and manufacture chips) and in-house proprietary fabrics, but it is differentiated by its focus and neutrality. EDA incumbents such as Cadence and Synopsys offer NoC-related IP as part of broader tool and IP portfolios, where interconnect is one component among many rather than a core specialization. Arteris is differentiated as an independent, interconnect-first specialist that avoids lock-in to any EDA stack, allowing customers to retain incumbent EDA workflows while integrating agnostic, high-performance NoC IP from Arteris. A deliberately reductive example: running Microsoft Windows while choosing Chrome over Edge.

Arteris’s leadership combines deep semiconductor, IP, and EDA experience. President and CEO K. Charles Janac has held the role since 2005, and has decades of leadership experience in semiconductor, EDA, and technology ventures. Laurent Moll, EVP Engineering and COO at Arteris, previously served as VP of Engineering at Qualcomm, where he led a 500-person team building core infrastructure IP including NoC IPs, and earlier held senior technical roles at Broadcom and Nvidia. Moll is a named inventor on more than 60 U.S. patents related to SoC technology and related IP. Across the team, there is a clear foundation of technical credibility and a track record of taking silicon-proven technology to market.

**What’s next?**

Arteris has positioned itself for relevance and future growth through alignment and ecosystem partnerships:

* **It works with Cadence** (CEO K. Charles Janac has notably worked at Cadence) to ensure tight integration with leading EDA flows, enabling customers to deploy Arteris IP without disrupting existing design toolchains.
* **It aligns with Arm ecosystems**, supporting standards such as AMBA so its NoCs can interoperate cleanly with Arm-based CPUs while remaining vendor-neutral.
* **It supports the RISC-V International ecosystem** (an open, royalty-free CPU instruction set), enabling vendor-neutral NoC integration for RISC-V–based SoCs alongside heterogeneous accelerators and chiplets.
* **It aligns its NoC IP with UCIe** (the emerging standard for die-to-die communication), where the NoC serves as the on-chip fabric that routes, arbitrates, and prioritizes UCIe traffic once it enters the SoC or SiP.
* **It joined the UALink Consortium**, which brings together AMD, Intel, Broadcom, Google, Meta, Cisco, and Microsoft to define an open, high-bandwidth interconnect standard for large-scale systems as an alternative to proprietary fabrics such as Nvidia’s NVLink/NVSwitch.

*As the neutral fabric underpinning data movement within chips and across chiplets, Arteris stands to benefit structurally as silicon design shifts toward modular, heterogeneous architectures in the chiplet era.*

Not investment advice. Reddit removes source hyperlinks. Do your own research and act accordingly.

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