ASCON-128 RTL(pure verilog)failing NIST test vectors

Anyone here implemented ASCON-128 in RTL?

My Verilog implementation fails the official NIST test vectors. I’ve tried bitsliced and non-bitsliced, and even checked multiple GitHub RTL repos, but none seem to pass the vectors as-is.

I’ve already checked:

endianness

padding / domain separation

round constants & permutation order

Outputs are consistently wrong, not random.

Is there a known issue with NIST test vectors vs HW implementations?
Any known-good RTL repo(that has been proven against the official NIST test vectors)or common parameter I might be missing?

Thanks